International Journal of Emerging Trends & Technology in Computer Science
A Motivation for Recent Innovation & Research
ISSN 2278-6856
www.ijettcs.org

Call for Paper, Published Articles, Indexing Infromation Implementation of 32-Bit Wave Pipelining Sparse Tree Adders, Authors : A.Padma Priya , M.Prema kumar, International Journal of Emerging Trends & Technology in Computer Science (IJETTCS), www.ijettcs.org
Volume & Issue no: Volume 3, Issue 5, September - October 2014

Title:
Implementation of 32-Bit Wave Pipelining Sparse Tree Adders
Author Name:
A.Padma Priya , M.Prema kumar
Abstract:
Abstract In this paper, we propose 32-bit parallel prefix sparse tree adder. In general N-bit adders like Ripple carry adders(slow adders compare to other adders), and carry lookahead adders(area consuming adders) are used in earlier days. But now the most of industries are using parallel prefix adders because of their advantages compare to other adder, The prefix sparse tree adders are faster and area efficient. Parallel prefix adder is a technique for increasing the speed in DSP processor while performing addition. We simulate and synthesis different types of 32-bit sparse tree adders using Xilinx ISE tool, By using these synthesis results, We noted the performanceparameters like number of LUT’s and delay. We compare these three adders interms of LUT’s represents area) and delay values.. Index terms: - digital arithmetic, carry skip adder, koggestone adder ,carry operator, prefix adder.
Cite this article:
A.Padma Priya , M.Prema kumar , " Implementation of 32-Bit Wave Pipelining Sparse Tree Adders " , International Journal of Emerging Trends & Technology in Computer Science (IJETTCS), Volume 3, Issue 5, September - October 2014 , pp. 212-216 , ISSN 2278-6856.
Full Text [PDF]                          Home