International Journal of Emerging Trends & Technology in Computer Science
A Motivation for Recent Innovation & Research
ISSN 2278-6856
www.ijettcs.org

Call for Paper, Published Articles, Indexing Infromation A REVIEW OF METHODOLOGIES FOR TESTING AND LOCATING FAULTS IN INTEGRATED CIRCUITS, Authors : R. H. Khade, D.S. Chaudhari, International Journal of Emerging Trends & Technology in Computer Science (IJETTCS), www.ijettcs.org
Volume & Issue no: Volume 3, Issue 6, November - December 2014

Title:
A REVIEW OF METHODOLOGIES FOR TESTING AND LOCATING FAULTS IN INTEGRATED CIRCUITS
Author Name:
R. H. Khade, D.S. Chaudhari
Abstract:
Abstract The recent advances in semiconductor integration technology resulted in manufacturing of very large number of components on a single chip. For reliable system-on-chip, the circuit should be fault free since a single fault is likely to make the whole chip useless. Locating the faults and application of corrective measures for same chip would reduce the running cost of the system. In this paper various works related to testing and locating faults in integrated circuits is reviewed. The literature related to digital and analog integrated circuits fault is considered. Based on the literature for various fault detecting methods, the oscillation based built-in self test (OBIST) method does not require stimulus generators or complex response analyzer and it is useful in testing analog and mixed-signal integrated circuits. Index Terms:- Built-in self-test (BIST), Circuit under test (CUT), Design for testability (DFT), Oscillation-based built-in self-test (OBIST), Path delay fault (PDF), Systemon- chips (SOCs), Test point insertion (TPI).
Cite this article:
R. H. Khade, D.S. Chaudhari , " A REVIEW OF METHODOLOGIES FOR TESTING AND LOCATING FAULTS IN INTEGRATED CIRCUITS " , International Journal of Emerging Trends & Technology in Computer Science (IJETTCS), Volume 3, Issue 6, November - December 2014 , pp. 239-241 , ISSN 2278-6856.
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